Embodiments of the invention relate to a thin film transistor, an array substrate, a manufacturing method of the array substrate, and a display panel.
Array substrate is an important component of a display panel. At present, low temperature poly-silicon (LTPS) material may be used to manufacture the array substrate. Due to problems in thermal process of LTPS, the array substrate generally adopts a top gate structure. FIG. 6 is a structural schematic view of a conventional array substrate. As shown in FIG. 6, the conventional array substrate comprises a substrate 17, and gate lines (not shown) and data lines 14 located on the array substrate. The gate lines and the data lines 14 cross with each other to define pixel regions. In each pixel region, there are formed a pixel electrode 18, a thin film transistor and a common electrode 19. The common electrode 19 forms a fringe electric field with the pixel electrode 18. The thin film transistor comprises an active layer pattern 10, a source electrode 11, a drain electrode 12 and a gate electrode 13. A buffer layer 21 is formed on the substrate 17. The active layer pattern 10 is formed on the buffer layer 21. The active layer pattern 10 comprises a channel region 10a, a lightly doped drain (LDD) region 10b, a source region 10c and a drain region 10d. The source region 10c and the drain region 10d are regions doped with impurity at a high concentration. The LDD region 10b is a region doped with impurity at a low concentration. A third insulation layer 22 is formed on the active layer pattern 10. The gate line and the gate electrode 13 are formed on the third insulation layer 22 at the same time, the gate line and the gate electrode 13 are connected with each other, and the gate electrode 13 is provided above the active layer pattern 10. A fourth insulation layer 23 is formed on the gate electrode 13. The pixel electrode 18 is formed on the fourth insulation layer 23. A first via hole 24 is formed in the third insulation layer 22 and the fourth insulation layer 23 above the active layer pattern 10, and the source electrode 11 is filled in the first via hole 24 to be connected with the active layer pattern 10. The source electrode 11 is also connected with the data line 14. A second via hole 25 is further formed in the third insulation layer 22 and the fourth insulation layer 23 above the active layer pattern 10, and the drain electrode 12 is filled in the second via hole 25 to be connected with the active layer pattern 10. The drain electrode 12 is partially provided on the pixel electrode 18 to be connected with the pixel electrode 18. A protection layer 26 is formed on the source electrode 11 and the drain electrode 12, and the common electrode 19 is formed on the protection layer 26.
As described above, in the conventional array substrate, the source electrode and the active layer pattern of the thin film transistor are connected with each other by via hole, and the drain electrode and the active layer pattern are also connected with each other by via hole. However, when via holes are formed in the pixel region, the aperture ratio of the pixel region is reduced.